A Very Large Scale Integration (VLSI) chip is generally composed of a silicon die having an integrated circuit printed thereon, a package for housing the silicon die that can be made of ceramic, organic or other types of chip carrier packages, and various means of electronic connection to the silicon die that extends to the exterior of the package for connection in an electronic system. Transistors and other circuit components reside on the silicon die in printed form and require power and signal connection extending to the exterior of the package. These connections would typically be coupled to a printed circuit board for further integration with other electronic components. The component features of the silicon die are extremely small, in the order of 0.1 to 1 micro-meter (Micron), whereas the features in the printed circuit board are in the order of 0.1 to 1 millimeter (mm). The connection configurations of a chip package bridge this large scaling gap by providing power and signal connections between the silicon die and the printed circuit board.
Referring to FIG. 1A, one configuration of a conventional chip package 100 is shown. The VLSI 102 is shown mounted on a ceramic base 104 and is connected via bond wires 106 to connection pins 108 through pin circuitry 112 of the chip package 100. The ceramic base 104 is coupled to the chip package 100 to dissipate heat from the VLSI 102 into the ambient outside the chip package 100. Also, the bond wires 106 are often a tenuous connection in the package 100 and are subject to defects. The connection pins 108 are configured to mount on a circuit board for further connection to other components.
Referring now to FIG. 1B, a top view of the chip package 100 is shown where bond wires 106 connect bonding pads 110 to the pin circuitry 112. As a result of manufacturing constraints, a design utilizing bond wires 106 such as in the chip package 100 have a limited access to pads 110 such that the pads 110 reside only on the periphery of the VLSI 102. Thus, the number of power and signal connections are greatly limited by the number of pads that can be accessed around the periphery of VLSI chip 102.
A second configuration of a conventional chip package 114 is shown in FIG. 1C. This configuration is known in the art as a "C-4 mount." In this configuration, the VLSI chip 116 is connected to the pin circuitry 118 via soldering bumps 120 located on the bottom surface of the VLSI chip 116. Here, the chip is inverted, or flipped, so that connections can be made to pins 108. As can be seen in Figure ID, this configuration allows a greater number of landing pads 122 on the surface of the VLSI chip 116 since the design is not limited to placing the landing pads on the periphery of the surface of VLSI 116. This solves the need for the increasing number of connections required to VLSI chips, particularly, microprocessors that have ever increasing demands for more signals and more power. An increase in the number of connections to the landing pads 122 allows for more signal lines and power lines to the VLSI chip. Also, the bond wires used in the design of FIG. 1 are eliminated. Details regarding one method of solder connections used in joining integrated semiconductor devices are found in related application "Multilayer Solder Interconnection Structure" of Mashimoto et al. cited above. Demands for higher power and more signals, however, continue to increase.
Every generation of VLSI chips continue to grow in complexity, performance and power consumption. As a result, the current demands for the chips also increase. One of the biggest challenges for future generations of chips is managing the chip's power consumption. Presently, the power consumption of a typical microprocessor is between 1 and 60 watts. As new generations of microprocessors are developed, however, the power demands are expected to increase into the hundreds or even thousands of watts as complexity of the chip increases and as better chip performance is demanded. Also, as more complicated microprocessors are developed, more transistors are used, the size of the silicon die grows and the signal frequency greatly increases. The net effect is that the power and current demands will continue to be major concerns in chip design.
One modern solution to manage increased power demand is voltage scaling. Voltage scaling is the process of reducing the voltage level of signals located inside and outside the VLSI chips so that less power is demanded. Power has a quadratic relationship to voltage where power is proportional to the square of the voltage. Hence, if the supply voltage is reduced by half, the power is reduced by one-fourth, giving a dramatic decrease in the power demand. Voltage scaling continues to be practiced in modern chip designs. For example, in the 1980's, the typical power supply voltage was 5 volts. Later in the 1990's, the average supply voltage was reduced to 3.3 volts. More modern designs have reduced the supply voltage to as low as 2.5 volts and even 1.8 volts. Voltage scaling, however, has its limits and the continuing increase in power and current demands are still inevitable.